Download Free Software Owon Oscilloscope Hack

Hacking the OWON SDS7102 Scope. A few years ago I bought myself an OWON SDS7102 oscilloscope. The specifications for the scope are rather nice: decent bandwidth and sampling rates, a large bright display, a battery option and lots of connectivity such as a. Save owon oscilloscope software to get e-mail alerts and updates on your eBay Feed. OWON SDS7102V 100Mhz Oscilloscope 1G/s 8' LAN VGA free firmware upgrade + VGA. New OWON 100Mhz Oscilloscope SDS7102 1G/s large 8' LCD LAN VGA included 3.

It is something of a rite of passage for an electronics enthusiast, the acquisition of a first oscilloscope. In decades past that usually meant a relatively modest instrument, maybe a 20MHz bandwidth and dual trace if you were lucky. Higher spec devices were eye-wateringly expensive monsters, not for the Common People. We are fortunate that like most other areas of technology the world of test equipment has benefited in the last few years both from developments in digital technology and from the growth in Chinese manufacturing. If your first ‘scope is that second-hand 20MHz CRT you will probably secure it for pennies, and the first ‘scope you buy new will probably have a spec closer to those unattainable super-scopes of yesteryear. Get link vip. Gone is the CRT and timebase generator, in its place a TFT, system-on-chip, and super-fast A to D converter.

[Christer Weinigel] has just such an entry-level modern digital ‘scope, an OWON SDS7102. He comments that it’s got an impressive spec for its price, though the input is noisier than you’d expect on a more expensive device, and the software has one or two annoying bugs. Having owned it for a while, he’s now subjected it to a lengthy teardown and reverse engineer,. [Christer]’s interest lay mainly in the OWON’s digital section, it seems there is already a substantial community paying attention to its analog front end. He’s deduced how its internals are connected, ported Linux to its Samsung SoC in the scope, succeeded in getting its peripherals working, and set to work programming the Xilinx FPGA that’s responsible for signal processing. The series of posts is a fascinating read as a run through the process of reverse engineering, but he points out that it’s quite a lot of information. If you are just interested in how a cheap modern oscilloscope works, he says, he suggests reading. He also makes a plea for help, he’s no slouch on the ‘scope’s software but admits he’s a bit out of his depth on some aspects of the FPGA.

If you’re an FPGA wizard with an interest in ‘scopes, he’d like to hear from you. This isn’t the first time we’ve featured ‘scope reverse engineering here at Hackaday, though it may be more in-depth than others. In the past we’ve seen a laid bare, and an investigation of a. • • • • Posted in Tagged,, Post navigation. The reverse engineering from the software and FPGA bitstream sides is stunning.

I really want to see all the gory details of the analog signal path including all the bits driving the ADC, clocking etc. But, I have a particular reason for this as part of my current project research. The FPGA stuff is not so hard(for me) but I admit, using the DDR2 interface on the SoC for the FPGA interconnect is pretty hardcore – I suspect the bandwidth through the simpler interfaces was not sufficient. It’s not like the Chinese to take the hard route just for the fun of it:D. I’m not really sure why they went with the DDR2 interface.

As you say, it has higher bandwidth (133MHz * 16 bits for the DDR bus instead of 67MHz * 16 bits for the peripheral bus) on the other hand the FPGA has to compete with the DDR memory for bandwidth. The DDR memory interface is also much more complex: instead of a read being a simple “here’s the address, give me the data” the CPU now has to do a precharge to open a memory row, read from the row and close the row; all this costs latency. I could imagine some the Owon having tricks in mind like letting the display controller in the SoC render graphics from the virtual DDR memory in the FPGA. That would probably not work if the FPGA is connected to the peripheral bus.

Displaying data directly from the FPGA that might allow some really nice “virtual phosphor” effects that would not be possible otherwise. On the other hand, the peripheral bus could be used to do DMA directly from the FPGA to the SoC main memory and that ought to be enough to let the FPGA update the display at 60Hz. It might be that the Owon engeineers having done a virtual DDR2 memory before and that is is a case of “if all you have is a hammer, everything looks like a nail”.